1. Field of the Invention
The invention relates to a semiconductor memory device such as ROM (read only memory).
This application is based on Patent Application No. Hei 09-204907 filed in Japan, the content of which is incorporated herein by reference.
2. Background Art
Conventionally, in this type of general semiconductor memory devices, a high speed reading means for reading data at specified addresses is provided, in which the reading is carried out by transition of addresses of data for a page decoder after reading a plurality of data in a memory cell matrix and transferred to a sense-amplifier circuit in parallel. Thus, a high speed reading operation is performed by transition of data addresses in a page access mode.
FIG. 11 is a block diagram showing a structure of a conventional four bit semiconductor memory device comprising a page access mode, as an example of ROM (read only memory) having the page access mode.
As shown in this figure, the conventional ROM is provided with an address buffer circuit 100, a CE buffer circuit 101, a memory cell matrix 107, an X-decoder 103, a Y-decoder 104, a Y-selector, a sense amplifier circuit 110, a page decoder 102, a sense amplifier selection circuit 150, and an output-buffer 113.
The address buffer circuit 100 receives address input signals ADo-ADn from the outside, and the CE buffer circuit 101 receives a control signal CE from the outside. The memory cell matrix 107 stores and holds memory data. The X-decoder 103 selects data along a word line direction of the memory cell matrix 107. The Y-decoder 104 and the Y-selector 108 select data along a digit line direction. The sense amplifier 110 reads and senses data information stored in the memory cell matrix 107, after pre-charging the digit line of the selected memory cell matrix 107 with an output control signal CEB of the CE buffer circuit 101.
The page decoder circuit 102 receives output address signals for the page access mode as an input signal and selects signals outputted from a plurality of sense amplifier circuits 110. The sense-amplifier selection circuit 150 selects output signals of the sense amplifier circuits 110 selected by the page-decoder circuit 102 and outputs selected signals. The output buffer 113 outputs data outputted from the selection circuit 150 to an output terminal 114.
Hereinafter a reading operation of a conventional memory device having four bits and having the page access mode is described.
In general, there are two types of read modes such as a normal access mode and a page access mode in reading functions of a semiconductor memory device having the page access mode, and an access function for reading data by rapidly switching the addresses is called a page access mode function.
First, the normal access mode is described.
The data reading operation using the normal access mode is performed by the following steps. After setting address input signals AD0 to ADn and a control signal CE from the outside into active states (active when the CEB signal is L), data in the 4 bit memory-cell-matrix are then read to four sense amplifier circuits 110, SA0 to SA3, in parallel, and one bit data selected using page addresses AD0 to ADn is then outputted. The first access time necessary in the normal access mode is designated as tACC or tCE.
Next, the page access mode is described.
The data reading operation using the page access mode is performed by the following steps. After the reading operation using the normal access mode is completed, by switching only page addresses AD0 and AD1, both output signals PSm (m=0, 1, 2, 3) of the page decoder 102 and output signals SAoutm (m=0, 1, 2, 3) of the sense amplifier circuits 110 which are selected by the page selection circuit 150 are processed through the output buffers 113, and data OUTn (n=0, 1, 2-n) are outputted to the output terminals 114. Since, in this case, the data reading operation is performed after data have been transferred and determined in the sense amplifier circuits, high speed reading is attained. The second access time necessary for reading using the page access mode is designated as tPAC. In general, the access time of tPAC is far faster than the access time using the normal access mode and it is possible to realize the access time tPAC in a range of 1/2 or 1/3 of that of tACC or tCE.
As described hereinbefore, in the conventional read circuit having a reading circuit using the page access mode, by activating a plurality of sense amplifier circuits, only the output signals SAoutm of the sense amplifier circuits 110 selected by the page selection circuit 150 are outputted to the output terminals 114 as data OUTn (n=0, 1, 2-n) by the aid of the later output buffer 113. Since it is necessary to maintain the output signals SAoutm of the sense amplifier circuits 110, which are not selected by the page selection circuit 150, in the standby state until they are transformed into the selection state, the current consumption in the sense amplifier circuits is large.
Here, a current waveform flowing in the sense amplifier circuits 110 is shown as ISA and ISAA in FIG. 12. ISA represents a current waveform for an access time corresponding to one sense amplifier 110, and ISAA represents a current waveform for an access time corresponding to one output. In conventional devices, since the device comprises sense amplifier circuits 110 having the same current capacity as that of the four bits page access mode, the relationship between ISA and ISAA is expressed as ISAA=4*(ISA), and ISAA is simply 4 times larger than ISA. Furthermore, the current waveform flowing in the sense amplifier circuits differs depending upon access modes, and, in general, there are three types of access modes. Current waveforms of sense amplifier circuits in different access modes will be described hereinafter.
The first access mode is a standby mode shown in the region tA1 and tA4 in FIG. 12, the second access mode is a normal access mode shown in the region of tA2, and the third access mode is a page access mode shown in the region of tA3. The regions tA1 and tA4 of the first timing are standby modes, and, in this case, a logic construction is provided such that a electric current does not flow.
The tA2 region of the second timing is the region of normal access mode. In this region, all of the sense amplifier circuits 110 are made active, and a pre-charging operation starts on a digit line selected by the Y-decoder 104 in the memory matrix 107 and the Y-selector 108, and a large electric current, which increases toward a peak current I1, flows in the sense amplifier circuits 110 in a partial region AI1 until the pre-charging operation is completed. A sum total of the electric current flowing within the partial region of AI1 corresponds to the quantity of electric charge of the digit line. Furthermore, a steady current I2 flows, since the active state is maintained after the pre-charging operation of the digit-line is completed. If the higher reading speeds tACC or tCE in the normal access mode are desired, they may be made possible by rise of the pre-charging capacity of the sense amplifier circuits 110. However, the rise in the pre-charging capacity accompanies an increase in the peak current I1 and the steady current I2 proportional to the data-reading speed tACC or tCE.
The tA3 region of the third timing is the region of a page access mode. Although no switching takes place in this region, the steady current I2 flows, since it is necessary to maintain the output signals of the sense amplifier circuits SAoutm in the standby state.
Hereinbefore, a description is given on currents flowing in one sense amplifier circuit 110 for each access mode. Total current ISAT flowing in all sense amplifier circuits can be expressed as; EQU ISAT=ISA*m*n
where, ISA is a current value flowing in a sense amplifier circuit, m is the page number of the sense amplifier circuit, and n is the number of outputted data. The number of the sense amplifier circuit is m*n. Therefore, by increasing the page number of the sense amplifier circuits m or the number of outputted data n, the peak current Ipmax and the steady current Ismax of the current ISAT flowing in the sense amplifier circuits 110 increase. Therefore, due to increases in the peak current Ipmax and the steady current Ismax, a fluctuation level of the power-source potential VCC and the ground potential GND increases. Moreover, recently, there is a tendency to increase the numbers of the page m and output data n to improve the function of memory devices.
Hereinbefore, a measure for controlling the page access mode operation of a conventional device which does not provide any means against increases of the peak and steady current was described as a first example of conventional methods. Other conventional control measures provided with means against increases in current are disclosed in Japanese Patent Application, First Publication No. Hei 8-55470 and Japanese Patent Application, First Publication No. Hei 7-211077. These measures will be described hereinafter, with brief comparison with the above first conventional measure, as the second and third conventional measures.
The second conventional measure disclosed in Japanese Patent Application, First Publication No. Hei 8-55470 is intended to reduce the current consumption by switching the driving capacity of a feedback-type inverter circuit in a biasing circuit, depending upon the access mode.
FIG. 13 is a block diagram illustrating a structure of a semiconductor memory device having, for example, a four bit page mode, as the second conventional example of ROMs comprising the page access mode. The difference between the first and second memory devices is in that the second memory device comprises two types of inverter circuit (circuit diagrams are not shown) having different driving capacities in the feedback inverter circuit in the biasing circuit for amplifying the potential of the digit line in the sense amplifier circuits 110, and that the driving capacity is controlled by switching the driving capacity of the sense amplifier circuits depending upon the access mode using a sense amplifier control circuit 106 provided between the address buffer circuit 100 and the sense amplifier circuits 110.
In this second structure, since a high speed reading is necessary when the reading is performed using the normal access mode, a feedback type inverter circuit with a high driving capacity is selected in the biasing circuit; and since high speed reading is not necessary when reading is performed using the page access mode, a feedback type inverter circuit with a small driving capacity in the biasing circuit is selected for amplifying the potential of the digit line of the sense amplifier circuits.
Next, timing waveforms are explained hereinafter referring to FIG. 14.
The differences between the waveforms of the second conventional example and the first conventional example are in the finishing time tSAPL of the pre-charging operation of data SAoutL read from the sense amplifier circuits 110 (region for the pre-charge operation is AI2), and in the peak current I1' and the stationary current I2' of the current waveform ISAL (shown by a dotted line). The finishing time tSAPL can be set in a range up to the cycle time tA2 of the normal access mode, because it is sufficient for the pre-charging operation to finish before the page decoder signal PSm is determined by the page access mode.
Consequently, the current ISAPL flowing in the sense amplifier circuits 110 during the normal access mode can be expressed as follows. Assuming that AI1 is a pre-charging operation region to pre-charge data SAoutF read from the sense amplifier circuits 110 using the normal access mode and that ISAF is a current waveform, and since the amount of the electric charge of each digit line is equal, the total sums of currents in both regions of AI1 and AI2 are identical, and the waveform ISAL is related with ISAF as AI1&lt;AI2, both peak currents I1' and the steady current I2' becomes small, and the reduced amounts of the peak current .DELTA.I1 and steady current .DELTA.I2 can be expressed as, .DELTA.I1=I1-I1' and .DELTA.I2=I2--I2'.
Therefore, the maximum value of the peak current in the current waveform Ipmax is expressed as, Ipmax=I2+3*I2'. When comparing this to the first conventional method, the reduced value of the peak current Ipmax in ISAA, .DELTA.Ipmax, and the reduced value of the steady current Ismax, .DELTA.Ismax, are expressed as, .DELTA.Ipmax=3*.DELTA.I1, and .DELTA.Ismax=3*Ismax. The above relationships clearly shows that the structure of the second device is constructed with a reduced current load.
Next, a third conventional example is described referring to the disclosure of Japanese Patent Application, First Publication No. Hei 7-211977. It is not necessary for the third conventional example to always activate the sense amplifier circuits, and since output signals from the sense amplifier circuits are determined at the time of normal access mode, sense amplifier circuits are controlled to convert into the non-active state after being latched by the latch circuit, so that the current consumption can be reduced.
FIG. 15 illustrates a constitution of a semiconductor memory device comprising a 4 bits page mode as the third example of conventional ROMs.
The third example differs from the first example in various points. That is, it comprises an address transition detector 105 (hereinafter, called as ATD) which detects transition of an output signal ao of the address buffer circuit 100 and outputs an one-shot-pulse signal at, and a sense amplifier control circuit 106 which receives the input signal of the one-shot-pulse signal at outputted from the ATD 105 and outputs a sense-amplifier control signal SAEB for controlling the activation/inactivation of the sense amplifier circuits 110 and a latch control signal LAEB for controlling the latch circuit 112. The sense amplifier control circuit 106 comprises a logic construction such that it is possible to control activation/inactivation of the sense amplifier circuits depending on the access mode.
Hereinafter, the third device will be explained referring to the timing waveform diagram shown in FIG. 16.
The third example differs from the first example in the timing of activation of the sense amplifier circuits 110. In the first conventional example, when the output signal CEB of the CE buffer circuit 101, which receives a control signal CE from outside, is in L-level, the sense amplifier circuits 110 are always activated during both the normal access mode (tA2 region) and the page access mode operations (tA3 region), and the sense amplifier circuits 110 are inactivated only when the output signal CEB of the CE buffer circuit is in the H-level (tA1 and tA4 regions). In contrast, in this third conventional example, a sense-amplifier control signal SAEB and a latch control signal LAED are outputted by the ATD 105 and the sense-amplifier control circuits 106 are activated such that only the area in the memory cell matrix for determine the reading data (in this case, L-level is the activated state). In access modes other than the normal access mode (in tA1, tA3, and tA4 regions), the sense-amplifier control signal SAEB and the latch control signal LAEB inactivate all sense amplifier circuits.
As hereinabove described, in the third conventional example comprising the page access mode, the operation of the sense amplifier circuits 110 in the normal access mode is the same as that of the first example, but after the sense-amplifier output signals SAoutm are determined, the circuit is maintained in the standby state, which results in a reduction of current consumption.
The current waveforms which flow in the sense amplifier circuits 110 are shown as ISA and ISAA in FIG. 16. ISA indicates a waveform corresponding to an access time of one sense amplifier 110, and ISAA corresponds to a total access time of one output. Since this convention example, similar to the first conventional example, is formed with the sense amplifier circuits having an identical capacity with that of the 4 bits page access mode, the relationship between ISA and ISAA can be expressed as, ISAA=4*(I SA), that is, ISAA is 4 times larger than ISA, and the waveforms ISAA and ISA are the same in the region tSAPF', where the sense amplifier circuits 110 are in the active state. However, the current does not flow in the sense amplifier circuits 110 in regions where the sense amplifier circuits 110 are not activated, after passing the activated region tSAPF'. Therefore, it is possible to further reduce the current consumption, compared with the first and second conventional examples.
Now, in the conventional semiconductor memory device having the page access function, since the sense amplifier circuits are activated simultaneously, the slope of current required to reach a high peak current becomes steep, and the level of fluctuation of the source potential VCC and the ground potential GND becomes large, which results in that the noise margin being deteriorated and the operational speed of the sense-amplifier circuits being reduced. This tendency becomes remarkable when the number of page and the number of bit increases.
A measure for this high peak current is shown in, for example, Japanese Patent Application, First Publication No. Hei 8-55470, which discloses a type of the sense-amplifier control circuit which switches and controls the driving capacity of the bias feedback circuit for amplifying the potential of the digit line in the sense amplifier circuits. Japanese Patent Application, First Publication No. Hei 7-211077 discloses another type of sense-amplifier control circuit which controls inactivation of the sense amplifier circuits when the reading is carried out using the page access mode. However, the above measures are not sufficient to solve the problem associated with the high peak current.